During operation of a data storage device, data may be communicated between a controller and a memory of the data storage device via a data bus that couples the controller and the memory. For example, one or more data values may be provided to or received from the data bus at a transfer rate based on a frequency of a clock signal. To illustrate, a first data value may be provided to the data bus from the controller in response to a rising edge of the clock signal. As another example, a second data value may be received from the data bus and stored at the controller in response to a falling edge of the clock signal.
A data storage device may be designed to have a fixed clock frequency that allows sufficient setup and hold times to enable reliable transmission and sampling of data over a bus interface between integrated circuits (e.g., a controller and a non-volatile memory). Typically, large margins are provided with respect to the clock frequency to account for worst-case scenarios (e.g., worst-case silicon process speed, system voltage, and system temperature (PVT) conditions) that may occur during operation of the data storage device. Setting the clock frequency (e.g., a data transfer rate) to the fixed value may avoid errors that may occur if the data transfer rate is too high in such worst-case scenarios. However, by operating the data storage device (e.g., the bus) at a clock frequency based on the worst-case scenarios, a data transfer rate (e.g., a bus speed) may be significantly lower than a theoretical maximum data transfer rate of the bus.